README

+
+The repository was moved to https://github.com/rhexsel/cmips
+
+This repo will not be updated.
+
+28th april 2017.
+
+
+
+
+
+
 cMIPS
 
 cMIPS is a synthesizable VHDL model for the 5-stage pipeline, MIPS32r2 core.
@@ -7,24 +19,27 @@ book (Computer Organisation and Design) and is a complete implementation
 of the MIPS32r2 instruction set.
 
 The model was synthesized for an Altera EP4CE30F23.  The model runs at 50 MHz
-(top board speed) and uses up 15% of the combinational blocks and 5% of the
-logic registers on the FPGA.
+(top board speed) and uses up 22% of the combinational blocks, 9% of the
+logic registers, and 33% of the memory bits on the FPGA.
 
-Processor model runs C code, compiled with GCC;  there are scripts to
-compile and assemble code to run on the simulator or the FPGA.
+The processor model runs C code, compiled with GCC;  there are scripts to
+compile and assemble code to run on the simulator or for sythesis.
 
-Core has all forwarding paths and full interlocks for data and control hazards.
+The core has all forwarding paths and is fully interlocked for data and
+control hazards.
 
 Coprocessor0 supports six hardware interrupts + NMI in "Interrupt
 Compatibility Mode" and an 8-way fully associative TLB.  The control
 instructions break, syscall, trap, mfc0, mtc0, eret, ei, di, ll, sc
 are fully implemented.
 
-Partial-word loads and stores (word, half-word, byte) implemented at the
-processor's memory interface.
+Partial-word loads and stores (word, half-word, byte, lwl,lwr,swl,swr) are
+implemented.
 
-Testbench for tests includes processor, RAM, ROM and (simulator) file I/O.
+A simulation testbench includes processor, RAM, ROM and (simulator) file I/O.
 
 Top level file for synthesis includes processor, RAM, ROM, LCD display
 controller, 2x7segment LED display, keypad and UART.  SDRAM controller,
 VGA interface and Ethernet port are in the works.
+
+See docs/cMIPS.pdf for a more complete description.
\ No newline at end of file

cMIPS/altera/alt_mf_rom.qip

+set_global_assignment -name IP_TOOL_NAME "ROM: 1-PORT"
+set_global_assignment -name IP_TOOL_VERSION "13.1"
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "alt_mf_rom.vhd"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "alt_mf_rom_inst.vhd"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "alt_mf_rom.cmp"]

cMIPS/altera/alt_mf_rom.vhd

+-- megafunction wizard: %ROM: 1-PORT%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: altsyncram 
+
+-- ============================================================
+-- File Name: alt_mf_rom.vhd
+-- Megafunction Name(s):
+-- 			altsyncram
+--
+-- Simulation Library Files(s):
+-- 			altera_mf
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 15.0.0 Build 145 04/22/2015 SJ Web Edition
+-- ************************************************************
+
+
+--Copyright (C) 1991-2015 Altera Corporation. All rights reserved.
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, the Altera Quartus II License Agreement,
+--the Altera MegaCore Function License Agreement, or other 
+--applicable license agreement, including, without limitation, 
+--that your use is for the sole purpose of programming logic 
+--devices manufactured by Altera and sold by Altera or its 
+--authorized distributors.  Please refer to the applicable 
+--agreement for further details.
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY altera_mf;
+USE altera_mf.altera_mf_components.all;
+
+ENTITY alt_mf_rom IS
+	PORT
+	(
+		address		: IN STD_LOGIC_VECTOR (12 DOWNTO 0);
+		clken		: IN STD_LOGIC  := '1';
+		clock		: IN STD_LOGIC  := '1';
+		q		: OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
+	);
+END alt_mf_rom;
+
+
+ARCHITECTURE SYN OF alt_mf_rom IS
+
+	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (31 DOWNTO 0);
+
+BEGIN
+	q    <= sub_wire0(31 DOWNTO 0);
+
+	altsyncram_component : altsyncram
+	GENERIC MAP (
+		address_aclr_a => "NONE",
+		clock_enable_input_a => "NORMAL",
+		clock_enable_output_a => "BYPASS",
+		init_file => "ROM.mif",
+		intended_device_family => "Cyclone IV E",
+		lpm_hint => "ENABLE_RUNTIME_MOD=NO",
+		lpm_type => "altsyncram",
+		numwords_a => 8192,
+		operation_mode => "ROM",
+		outdata_aclr_a => "NONE",
+		outdata_reg_a => "UNREGISTERED",
+		widthad_a => 13,
+		width_a => 32,
+		width_byteena_a => 1
+	)
+	PORT MAP (
+		address_a => address,
+		clock0 => clock,
+		clocken0 => clken,
+		q_a => sub_wire0
+	);
+
+
+
+END SYN;
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
+-- Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
+-- Retrieval info: PRIVATE: AclrByte NUMERIC "0"
+-- Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
+-- Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
+-- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
+-- Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
+-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "1"
+-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
+-- Retrieval info: PRIVATE: Clken NUMERIC "1"
+-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
+-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
+-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
+-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
+-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
+-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
+-- Retrieval info: PRIVATE: MIFfilename STRING "ROM.mif"
+-- Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "8192"
+-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
+-- Retrieval info: PRIVATE: RegAddr NUMERIC "1"
+-- Retrieval info: PRIVATE: RegOutput NUMERIC "0"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: PRIVATE: SingleClock NUMERIC "1"
+-- Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
+-- Retrieval info: PRIVATE: WidthAddr NUMERIC "13"
+-- Retrieval info: PRIVATE: WidthData NUMERIC "32"
+-- Retrieval info: PRIVATE: rden NUMERIC "0"
+-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+-- Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"
+-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "NORMAL"
+-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
+-- Retrieval info: CONSTANT: INIT_FILE STRING "ROM.mif"
+-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
+-- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
+-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "8192"
+-- Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
+-- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
+-- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
+-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "13"
+-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "32"
+-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
+-- Retrieval info: USED_PORT: address 0 0 13 0 INPUT NODEFVAL "address[12..0]"
+-- Retrieval info: USED_PORT: clken 0 0 0 0 INPUT VCC "clken"
+-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
+-- Retrieval info: USED_PORT: q 0 0 32 0 OUTPUT NODEFVAL "q[31..0]"
+-- Retrieval info: CONNECT: @address_a 0 0 13 0 address 0 0 13 0
+-- Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
+-- Retrieval info: CONNECT: @clocken0 0 0 0 0 clken 0 0 0 0
+-- Retrieval info: CONNECT: q 0 0 32 0 @q_a 0 0 32 0
+-- Retrieval info: GEN_FILE: TYPE_NORMAL alt_mf_rom.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL alt_mf_rom.inc FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL alt_mf_rom.cmp TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL alt_mf_rom.bsf FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL alt_mf_rom_inst.vhd TRUE
+-- Retrieval info: LIB_FILE: altera_mf

cMIPS/altera/mf_alt_add_4.qip

+set_global_assignment -name IP_TOOL_NAME "LPM_ADD_SUB"
+set_global_assignment -name IP_TOOL_VERSION "13.1"
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "mf_alt_add_4.vhd"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "mf_alt_add_4_inst.vhd"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "mf_alt_add_4.cmp"]

cMIPS/altera/mf_alt_add_4.vhd

+-- megafunction wizard: %LPM_ADD_SUB%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: LPM_ADD_SUB 
+
+-- ============================================================
+-- File Name: mf_alt_add_4.vhd
+-- Megafunction Name(s):
+-- 			LPM_ADD_SUB
+--
+-- Simulation Library Files(s):
+-- 			lpm
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 13.1.0 Build 162 10/23/2013 SJ Web Edition
+-- ************************************************************
+
+
+--Copyright (C) 1991-2013 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY lpm;
+USE lpm.all;
+
+ENTITY mf_alt_add_4 IS
+	PORT
+	(
+		datab		: IN STD_LOGIC_VECTOR (31 DOWNTO 0);
+		result		: OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
+	);
+END mf_alt_add_4;
+
+
+ARCHITECTURE SYN OF mf_alt_add_4 IS
+
+	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (31 DOWNTO 0);
+	SIGNAL sub_wire1_bv	: BIT_VECTOR (31 DOWNTO 0);
+	SIGNAL sub_wire1	: STD_LOGIC_VECTOR (31 DOWNTO 0);
+
+
+
+	COMPONENT lpm_add_sub
+	GENERIC (
+		lpm_direction		: STRING;
+		lpm_hint		: STRING;
+		lpm_representation		: STRING;
+		lpm_type		: STRING;
+		lpm_width		: NATURAL
+	);
+	PORT (
+			dataa	: IN STD_LOGIC_VECTOR (31 DOWNTO 0);
+			datab	: IN STD_LOGIC_VECTOR (31 DOWNTO 0);
+			result	: OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
+	);
+	END COMPONENT;
+
+BEGIN
+	sub_wire1_bv(31 DOWNTO 0) <= "00000000000000000000000000000100";
+	sub_wire1    <= To_stdlogicvector(sub_wire1_bv);
+	result    <= sub_wire0(31 DOWNTO 0);
+
+	LPM_ADD_SUB_component : LPM_ADD_SUB
+	GENERIC MAP (
+		lpm_direction => "ADD",
+		lpm_hint => "ONE_INPUT_IS_CONSTANT=YES,CIN_USED=NO",
+		lpm_representation => "SIGNED",
+		lpm_type => "LPM_ADD_SUB",
+		lpm_width => 32
+	)
+	PORT MAP (
+		dataa => sub_wire1,
+		datab => datab,
+		result => sub_wire0
+	);
+
+
+
+END SYN;
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: CarryIn NUMERIC "0"
+-- Retrieval info: PRIVATE: CarryOut NUMERIC "0"
+-- Retrieval info: PRIVATE: ConstantA NUMERIC "4"
+-- Retrieval info: PRIVATE: ConstantB NUMERIC "0"
+-- Retrieval info: PRIVATE: Function NUMERIC "0"
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
+-- Retrieval info: PRIVATE: LPM_PIPELINE NUMERIC "0"
+-- Retrieval info: PRIVATE: Latency NUMERIC "0"
+-- Retrieval info: PRIVATE: Overflow NUMERIC "0"
+-- Retrieval info: PRIVATE: RadixA NUMERIC "10"
+-- Retrieval info: PRIVATE: RadixB NUMERIC "10"
+-- Retrieval info: PRIVATE: Representation NUMERIC "0"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: PRIVATE: ValidCtA NUMERIC "1"
+-- Retrieval info: PRIVATE: ValidCtB NUMERIC "0"
+-- Retrieval info: PRIVATE: WhichConstant NUMERIC "1"
+-- Retrieval info: PRIVATE: aclr NUMERIC "0"
+-- Retrieval info: PRIVATE: clken NUMERIC "0"
+-- Retrieval info: PRIVATE: nBit NUMERIC "32"
+-- Retrieval info: PRIVATE: new_diagram STRING "1"
+-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
+-- Retrieval info: CONSTANT: LPM_DIRECTION STRING "ADD"
+-- Retrieval info: CONSTANT: LPM_HINT STRING "ONE_INPUT_IS_CONSTANT=YES,CIN_USED=NO"
+-- Retrieval info: CONSTANT: LPM_REPRESENTATION STRING "SIGNED"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_ADD_SUB"
+-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "32"
+-- Retrieval info: USED_PORT: datab 0 0 32 0 INPUT NODEFVAL "datab[31..0]"
+-- Retrieval info: USED_PORT: result 0 0 32 0 OUTPUT NODEFVAL "result[31..0]"
+-- Retrieval info: CONNECT: @dataa 0 0 32 0 4 0 0 32 0
+-- Retrieval info: CONNECT: @datab 0 0 32 0 datab 0 0 32 0
+-- Retrieval info: CONNECT: result 0 0 32 0 @result 0 0 32 0
+-- Retrieval info: GEN_FILE: TYPE_NORMAL mf_alt_add_4.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL mf_alt_add_4.inc FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL mf_alt_add_4.cmp TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL mf_alt_add_4.bsf FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL mf_alt_add_4_inst.vhd TRUE
+-- Retrieval info: LIB_FILE: lpm

cMIPS/altera/mf_alt_add_4_inst.vhd

+mf_alt_add_4_inst : mf_alt_add_4 PORT MAP (
+		datab	 => datab_sig,
+		result	 => result_sig
+	);

cMIPS/altera/mf_alt_add_sub.qip

+set_global_assignment -name IP_TOOL_NAME "LPM_ADD_SUB"
+set_global_assignment -name IP_TOOL_VERSION "13.1"
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "mf_alt_add_sub.vhd"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "mf_alt_add_sub_inst.vhd"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "mf_alt_add_sub.cmp"]

cMIPS/altera/mf_alt_add_sub.vhd

+-- megafunction wizard: %LPM_ADD_SUB%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: LPM_ADD_SUB 
+
+-- ============================================================
+-- File Name: mf_alt_add_sub.vhd
+-- Megafunction Name(s):
+-- 			LPM_ADD_SUB
+--
+-- Simulation Library Files(s):
+-- 			lpm
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 13.1.0 Build 162 10/23/2013 SJ Web Edition
+-- ************************************************************
+
+
+--Copyright (C) 1991-2013 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY lpm;
+USE lpm.all;
+
+ENTITY mf_alt_add_sub IS
+	PORT
+	(
+		add_sub		: IN STD_LOGIC ;
+		dataa		: IN STD_LOGIC_VECTOR (31 DOWNTO 0);
+		datab		: IN STD_LOGIC_VECTOR (31 DOWNTO 0);
+		overflow		: OUT STD_LOGIC ;
+		result		: OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
+	);
+END mf_alt_add_sub;
+
+
+ARCHITECTURE SYN OF mf_alt_add_sub IS
+
+	SIGNAL sub_wire0	: STD_LOGIC ;
+	SIGNAL sub_wire1	: STD_LOGIC_VECTOR (31 DOWNTO 0);
+
+
+
+	COMPONENT lpm_add_sub
+	GENERIC (
+		lpm_direction		: STRING;
+		lpm_hint		: STRING;
+		lpm_representation		: STRING;
+		lpm_type		: STRING;
+		lpm_width		: NATURAL
+	);
+	PORT (
+			add_sub	: IN STD_LOGIC ;
+			datab	: IN STD_LOGIC_VECTOR (31 DOWNTO 0);
+			overflow	: OUT STD_LOGIC ;
+			dataa	: IN STD_LOGIC_VECTOR (31 DOWNTO 0);
+			result	: OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
+	);
+	END COMPONENT;
+
+BEGIN
+	overflow    <= sub_wire0;
+	result    <= sub_wire1(31 DOWNTO 0);
+
+	LPM_ADD_SUB_component : LPM_ADD_SUB
+	GENERIC MAP (
+		lpm_direction => "UNUSED",
+		lpm_hint => "ONE_INPUT_IS_CONSTANT=NO,CIN_USED=NO",
+		lpm_representation => "SIGNED",
+		lpm_type => "LPM_ADD_SUB",
+		lpm_width => 32
+	)
+	PORT MAP (
+		add_sub => add_sub,
+		datab => datab,
+		dataa => dataa,
+		overflow => sub_wire0,
+		result => sub_wire1
+	);
+
+
+
+END SYN;
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: CarryIn NUMERIC "0"
+-- Retrieval info: PRIVATE: CarryOut NUMERIC "0"
+-- Retrieval info: PRIVATE: ConstantA NUMERIC "0"
+-- Retrieval info: PRIVATE: ConstantB NUMERIC "0"
+-- Retrieval info: PRIVATE: Function NUMERIC "2"
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
+-- Retrieval info: PRIVATE: LPM_PIPELINE NUMERIC "0"
+-- Retrieval info: PRIVATE: Latency NUMERIC "0"
+-- Retrieval info: PRIVATE: Overflow NUMERIC "1"
+-- Retrieval info: PRIVATE: RadixA NUMERIC "10"
+-- Retrieval info: PRIVATE: RadixB NUMERIC "10"
+-- Retrieval info: PRIVATE: Representation NUMERIC "0"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: PRIVATE: ValidCtA NUMERIC "0"
+-- Retrieval info: PRIVATE: ValidCtB NUMERIC "0"
+-- Retrieval info: PRIVATE: WhichConstant NUMERIC "0"
+-- Retrieval info: PRIVATE: aclr NUMERIC "0"
+-- Retrieval info: PRIVATE: clken NUMERIC "0"
+-- Retrieval info: PRIVATE: nBit NUMERIC "32"
+-- Retrieval info: PRIVATE: new_diagram STRING "1"
+-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
+-- Retrieval info: CONSTANT: LPM_DIRECTION STRING "UNUSED"
+-- Retrieval info: CONSTANT: LPM_HINT STRING "ONE_INPUT_IS_CONSTANT=NO,CIN_USED=NO"
+-- Retrieval info: CONSTANT: LPM_REPRESENTATION STRING "SIGNED"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_ADD_SUB"
+-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "32"
+-- Retrieval info: USED_PORT: add_sub 0 0 0 0 INPUT NODEFVAL "add_sub"
+-- Retrieval info: USED_PORT: dataa 0 0 32 0 INPUT NODEFVAL "dataa[31..0]"
+-- Retrieval info: USED_PORT: datab 0 0 32 0 INPUT NODEFVAL "datab[31..0]"
+-- Retrieval info: USED_PORT: overflow 0 0 0 0 OUTPUT NODEFVAL "overflow"
+-- Retrieval info: USED_PORT: result 0 0 32 0 OUTPUT NODEFVAL "result[31..0]"
+-- Retrieval info: CONNECT: @add_sub 0 0 0 0 add_sub 0 0 0 0
+-- Retrieval info: CONNECT: @dataa 0 0 32 0 dataa 0 0 32 0
+-- Retrieval info: CONNECT: @datab 0 0 32 0 datab 0 0 32 0
+-- Retrieval info: CONNECT: overflow 0 0 0 0 @overflow 0 0 0 0
+-- Retrieval info: CONNECT: result 0 0 32 0 @result 0 0 32 0
+-- Retrieval info: GEN_FILE: TYPE_NORMAL mf_alt_add_sub.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL mf_alt_add_sub.inc FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL mf_alt_add_sub.cmp TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL mf_alt_add_sub.bsf FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL mf_alt_add_sub_inst.vhd TRUE
+-- Retrieval info: LIB_FILE: lpm

cMIPS/altera/mf_alt_add_sub_inst.vhd

+mf_alt_add_sub_inst : mf_alt_add_sub PORT MAP (
+		add_sub	 => add_sub_sig,
+		dataa	 => dataa_sig,
+		datab	 => datab_sig,
+		overflow	 => overflow_sig,
+		result	 => result_sig
+	);

cMIPS/altera/mf_alt_add_sub_u.qip

+set_global_assignment -name IP_TOOL_NAME "LPM_ADD_SUB"
+set_global_assignment -name IP_TOOL_VERSION "13.1"
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "mf_alt_add_sub_u.vhd"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "mf_alt_add_sub_u_inst.vhd"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "mf_alt_add_sub_u.cmp"]

cMIPS/altera/mf_alt_add_sub_u.vhd

+-- megafunction wizard: %LPM_ADD_SUB%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: LPM_ADD_SUB 
+
+-- ============================================================
+-- File Name: mf_alt_add_sub_u.vhd
+-- Megafunction Name(s):
+-- 			LPM_ADD_SUB
+--
+-- Simulation Library Files(s):
+-- 			lpm
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 13.1.0 Build 162 10/23/2013 SJ Web Edition
+-- ************************************************************
+
+
+--Copyright (C) 1991-2013 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY lpm;
+USE lpm.all;
+
+ENTITY mf_alt_add_sub_u IS
+	PORT
+	(
+		add_sub		: IN STD_LOGIC ;
+		dataa		: IN STD_LOGIC_VECTOR (31 DOWNTO 0);
+		datab		: IN STD_LOGIC_VECTOR (31 DOWNTO 0);
+		result		: OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
+	);
+END mf_alt_add_sub_u;
+
+
+ARCHITECTURE SYN OF mf_alt_add_sub_u IS
+
+	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (31 DOWNTO 0);
+
+
+
+	COMPONENT lpm_add_sub
+	GENERIC (
+		lpm_direction		: STRING;
+		lpm_hint		: STRING;
+		lpm_representation		: STRING;
+		lpm_type		: STRING;
+		lpm_width		: NATURAL
+	);
+	PORT (
+			add_sub	: IN STD_LOGIC ;
+			dataa	: IN STD_LOGIC_VECTOR (31 DOWNTO 0);
+			datab	: IN STD_LOGIC_VECTOR (31 DOWNTO 0);
+			result	: OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
+	);
+	END COMPONENT;
+
+BEGIN
+	result    <= sub_wire0(31 DOWNTO 0);
+
+	LPM_ADD_SUB_component : LPM_ADD_SUB
+	GENERIC MAP (
+		lpm_direction => "UNUSED",
+		lpm_hint => "ONE_INPUT_IS_CONSTANT=NO,CIN_USED=NO",
+		lpm_representation => "UNSIGNED",
+		lpm_type => "LPM_ADD_SUB",
+		lpm_width => 32
+	)
+	PORT MAP (
+		add_sub => add_sub,
+		dataa => dataa,
+		datab => datab,
+		result => sub_wire0
+	);
+
+
+
+END SYN;
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: CarryIn NUMERIC "0"
+-- Retrieval info: PRIVATE: CarryOut NUMERIC "0"
+-- Retrieval info: PRIVATE: ConstantA NUMERIC "0"
+-- Retrieval info: PRIVATE: ConstantB NUMERIC "0"
+-- Retrieval info: PRIVATE: Function NUMERIC "2"
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
+-- Retrieval info: PRIVATE: LPM_PIPELINE NUMERIC "0"
+-- Retrieval info: PRIVATE: Latency NUMERIC "0"
+-- Retrieval info: PRIVATE: Overflow NUMERIC "0"
+-- Retrieval info: PRIVATE: RadixA NUMERIC "10"
+-- Retrieval info: PRIVATE: RadixB NUMERIC "10"
+-- Retrieval info: PRIVATE: Representation NUMERIC "1"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: PRIVATE: ValidCtA NUMERIC "0"
+-- Retrieval info: PRIVATE: ValidCtB NUMERIC "0"
+-- Retrieval info: PRIVATE: WhichConstant NUMERIC "0"
+-- Retrieval info: PRIVATE: aclr NUMERIC "0"
+-- Retrieval info: PRIVATE: clken NUMERIC "0"
+-- Retrieval info: PRIVATE: nBit NUMERIC "32"
+-- Retrieval info: PRIVATE: new_diagram STRING "1"
+-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
+-- Retrieval info: CONSTANT: LPM_DIRECTION STRING "UNUSED"
+-- Retrieval info: CONSTANT: LPM_HINT STRING "ONE_INPUT_IS_CONSTANT=NO,CIN_USED=NO"
+-- Retrieval info: CONSTANT: LPM_REPRESENTATION STRING "UNSIGNED"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_ADD_SUB"
+-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "32"
+-- Retrieval info: USED_PORT: add_sub 0 0 0 0 INPUT NODEFVAL "add_sub"
+-- Retrieval info: USED_PORT: dataa 0 0 32 0 INPUT NODEFVAL "dataa[31..0]"
+-- Retrieval info: USED_PORT: datab 0 0 32 0 INPUT NODEFVAL "datab[31..0]"
+-- Retrieval info: USED_PORT: result 0 0 32 0 OUTPUT NODEFVAL "result[31..0]"
+-- Retrieval info: CONNECT: @add_sub 0 0 0 0 add_sub 0 0 0 0
+-- Retrieval info: CONNECT: @dataa 0 0 32 0 dataa 0 0 32 0
+-- Retrieval info: CONNECT: @datab 0 0 32 0 datab 0 0 32 0
+-- Retrieval info: CONNECT: result 0 0 32 0 @result 0 0 32 0
+-- Retrieval info: GEN_FILE: TYPE_NORMAL mf_alt_add_sub_u.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL mf_alt_add_sub_u.inc FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL mf_alt_add_sub_u.cmp TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL mf_alt_add_sub_u.bsf FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL mf_alt_add_sub_u_inst.vhd TRUE
+-- Retrieval info: LIB_FILE: lpm

cMIPS/altera/mf_alt_add_sub_u_inst.vhd

+mf_alt_add_sub_u_inst : mf_alt_add_sub_u PORT MAP (
+		add_sub	 => add_sub_sig,
+		dataa	 => dataa_sig,
+		datab	 => datab_sig,
+		result	 => result_sig
+	);

cMIPS/altera/mf_alt_adder.qip

+set_global_assignment -name IP_TOOL_NAME "LPM_ADD_SUB"
+set_global_assignment -name IP_TOOL_VERSION "13.1"
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "mf_alt_adder.vhd"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "mf_alt_adder_inst.vhd"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "mf_alt_adder.cmp"]

cMIPS/altera/mf_alt_adder.vhd

+-- megafunction wizard: %LPM_ADD_SUB%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: LPM_ADD_SUB 
+
+-- ============================================================
+-- File Name: mf_alt_adder.vhd
+-- Megafunction Name(s):
+-- 			LPM_ADD_SUB
+--
+-- Simulation Library Files(s):
+-- 			lpm
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 13.1.0 Build 162 10/23/2013 SJ Web Edition
+-- ************************************************************
+
+
+--Copyright (C) 1991-2013 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY lpm;
+USE lpm.all;
+
+ENTITY mf_alt_adder IS
+	PORT
+	(
+		dataa		: IN STD_LOGIC_VECTOR (31 DOWNTO 0);
+		datab		: IN STD_LOGIC_VECTOR (31 DOWNTO 0);
+		result		: OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
+	);
+END mf_alt_adder;
+
+
+ARCHITECTURE SYN OF mf_alt_adder IS
+
+	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (31 DOWNTO 0);
+
+
+
+	COMPONENT lpm_add_sub
+	GENERIC (
+		lpm_direction		: STRING;
+		lpm_hint		: STRING;
+		lpm_representation		: STRING;
+		lpm_type		: STRING;
+		lpm_width		: NATURAL
+	);
+	PORT (
+			dataa	: IN STD_LOGIC_VECTOR (31 DOWNTO 0);
+			datab	: IN STD_LOGIC_VECTOR (31 DOWNTO 0);
+			result	: OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
+	);
+	END COMPONENT;
+
+BEGIN
+	result    <= sub_wire0(31 DOWNTO 0);
+
+	LPM_ADD_SUB_component : LPM_ADD_SUB
+	GENERIC MAP (
+		lpm_direction => "ADD",
+		lpm_hint => "ONE_INPUT_IS_CONSTANT=NO,CIN_USED=NO",
+		lpm_representation => "SIGNED",
+		lpm_type => "LPM_ADD_SUB",
+		lpm_width => 32
+	)
+	PORT MAP (
+		dataa => dataa,
+		datab => datab,
+		result => sub_wire0
+	);
+
+
+
+END SYN;
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: CarryIn NUMERIC "0"
+-- Retrieval info: PRIVATE: CarryOut NUMERIC "0"
+-- Retrieval info: PRIVATE: ConstantA NUMERIC "0"
+-- Retrieval info: PRIVATE: ConstantB NUMERIC "0"
+-- Retrieval info: PRIVATE: Function NUMERIC "0"
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
+-- Retrieval info: PRIVATE: LPM_PIPELINE NUMERIC "0"
+-- Retrieval info: PRIVATE: Latency NUMERIC "0"
+-- Retrieval info: PRIVATE: Overflow NUMERIC "0"
+-- Retrieval info: PRIVATE: RadixA NUMERIC "10"
+-- Retrieval info: PRIVATE: RadixB NUMERIC "10"
+-- Retrieval info: PRIVATE: Representation NUMERIC "0"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: PRIVATE: ValidCtA NUMERIC "0"
+-- Retrieval info: PRIVATE: ValidCtB NUMERIC "0"
+-- Retrieval info: PRIVATE: WhichConstant NUMERIC "0"
+-- Retrieval info: PRIVATE: aclr NUMERIC "0"
+-- Retrieval info: PRIVATE: clken NUMERIC "0"
+-- Retrieval info: PRIVATE: nBit NUMERIC "32"
+-- Retrieval info: PRIVATE: new_diagram STRING "1"
+-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
+-- Retrieval info: CONSTANT: LPM_DIRECTION STRING "ADD"
+-- Retrieval info: CONSTANT: LPM_HINT STRING "ONE_INPUT_IS_CONSTANT=NO,CIN_USED=NO"
+-- Retrieval info: CONSTANT: LPM_REPRESENTATION STRING "SIGNED"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_ADD_SUB"
+-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "32"
+-- Retrieval info: USED_PORT: dataa 0 0 32 0 INPUT NODEFVAL "dataa[31..0]"
+-- Retrieval info: USED_PORT: datab 0 0 32 0 INPUT NODEFVAL "datab[31..0]"
+-- Retrieval info: USED_PORT: result 0 0 32 0 OUTPUT NODEFVAL "result[31..0]"
+-- Retrieval info: CONNECT: @dataa 0 0 32 0 dataa 0 0 32 0
+-- Retrieval info: CONNECT: @datab 0 0 32 0 datab 0 0 32 0
+-- Retrieval info: CONNECT: result 0 0 32 0 @result 0 0 32 0
+-- Retrieval info: GEN_FILE: TYPE_NORMAL mf_alt_adder.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL mf_alt_adder.inc FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL mf_alt_adder.cmp TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL mf_alt_adder.bsf FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL mf_alt_adder_inst.vhd TRUE
+-- Retrieval info: LIB_FILE: lpm

cMIPS/altera/mf_alt_adder_inst.vhd

+mf_alt_adder_inst : mf_alt_adder PORT MAP (
+		dataa	 => dataa_sig,
+		datab	 => datab_sig,
+		result	 => result_sig
+	);

cMIPS/altera/mf_alt_subtr.qip

+set_global_assignment -name IP_TOOL_NAME "LPM_ADD_SUB"
+set_global_assignment -name IP_TOOL_VERSION "13.1"
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "mf_alt_subtr.vhd"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "mf_alt_subtr_inst.vhd"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "mf_alt_subtr.cmp"]

cMIPS/altera/mf_alt_subtr.vhd

+-- megafunction wizard: %LPM_ADD_SUB%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: LPM_ADD_SUB 
+
+-- ============================================================
+-- File Name: mf_alt_subtr.vhd
+-- Megafunction Name(s):
+-- 			LPM_ADD_SUB
+--
+-- Simulation Library Files(s):
+-- 			lpm
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 13.1.0 Build 162 10/23/2013 SJ Web Edition
+-- ************************************************************
+
+
+--Copyright (C) 1991-2013 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY lpm;
+USE lpm.all;
+
+ENTITY mf_alt_subtr IS
+	PORT
+	(
+		dataa		: IN STD_LOGIC_VECTOR (31 DOWNTO 0);
+		datab		: IN STD_LOGIC_VECTOR (31 DOWNTO 0);
+		overflow		: OUT STD_LOGIC ;
+		result		: OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
+	);
+END mf_alt_subtr;
+
+
+ARCHITECTURE SYN OF mf_alt_subtr IS
+
+	SIGNAL sub_wire0	: STD_LOGIC ;
+	SIGNAL sub_wire1	: STD_LOGIC_VECTOR (31 DOWNTO 0);
+
+
+
+	COMPONENT lpm_add_sub
+	GENERIC (
+		lpm_direction		: STRING;
+		lpm_hint		: STRING;
+		lpm_representation		: STRING;
+		lpm_type		: STRING;
+		lpm_width		: NATURAL
+	);
+	PORT (
+			dataa	: IN STD_LOGIC_VECTOR (31 DOWNTO 0);
+			datab	: IN STD_LOGIC_VECTOR (31 DOWNTO 0);
+			overflow	: OUT STD_LOGIC ;
+			result	: OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
+	);
+	END COMPONENT;
+
+BEGIN
+	overflow    <= sub_wire0;
+	result    <= sub_wire1(31 DOWNTO 0);
+
+	LPM_ADD_SUB_component : LPM_ADD_SUB
+	GENERIC MAP (
+		lpm_direction => "SUB",
+		lpm_hint => "ONE_INPUT_IS_CONSTANT=NO,CIN_USED=NO",
+		lpm_representation => "UNSIGNED",
+		lpm_type => "LPM_ADD_SUB",
+		lpm_width => 32
+	)
+	PORT MAP (
+		dataa => dataa,
+		datab => datab,
+		overflow => sub_wire0,
+		result => sub_wire1
+	);
+
+
+
+END SYN;
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: CarryIn NUMERIC "0"
+-- Retrieval info: PRIVATE: CarryOut NUMERIC "0"
+-- Retrieval info: PRIVATE: ConstantA NUMERIC "0"
+-- Retrieval info: PRIVATE: ConstantB NUMERIC "0"
+-- Retrieval info: PRIVATE: Function NUMERIC "1"
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
+-- Retrieval info: PRIVATE: LPM_PIPELINE NUMERIC "0"
+-- Retrieval info: PRIVATE: Latency NUMERIC "0"
+-- Retrieval info: PRIVATE: Overflow NUMERIC "1"
+-- Retrieval info: PRIVATE: RadixA NUMERIC "10"
+-- Retrieval info: PRIVATE: RadixB NUMERIC "10"
+-- Retrieval info: PRIVATE: Representation NUMERIC "1"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: PRIVATE: ValidCtA NUMERIC "0"
+-- Retrieval info: PRIVATE: ValidCtB NUMERIC "0"
+-- Retrieval info: PRIVATE: WhichConstant NUMERIC "0"
+-- Retrieval info: PRIVATE: aclr NUMERIC "0"
+-- Retrieval info: PRIVATE: clken NUMERIC "0"
+-- Retrieval info: PRIVATE: nBit NUMERIC "32"
+-- Retrieval info: PRIVATE: new_diagram STRING "1"
+-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
+-- Retrieval info: CONSTANT: LPM_DIRECTION STRING "SUB"
+-- Retrieval info: CONSTANT: LPM_HINT STRING "ONE_INPUT_IS_CONSTANT=NO,CIN_USED=NO"
+-- Retrieval info: CONSTANT: LPM_REPRESENTATION STRING "UNSIGNED"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_ADD_SUB"
+-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "32"
+-- Retrieval info: USED_PORT: dataa 0 0 32 0 INPUT NODEFVAL "dataa[31..0]"
+-- Retrieval info: USED_PORT: datab 0 0 32 0 INPUT NODEFVAL "datab[31..0]"
+-- Retrieval info: USED_PORT: overflow 0 0 0 0 OUTPUT NODEFVAL "overflow"
+-- Retrieval info: USED_PORT: result 0 0 32 0 OUTPUT NODEFVAL "result[31..0]"
+-- Retrieval info: CONNECT: @dataa 0 0 32 0 dataa 0 0 32 0
+-- Retrieval info: CONNECT: @datab 0 0 32 0 datab 0 0 32 0
+-- Retrieval info: CONNECT: overflow 0 0 0 0 @overflow 0 0 0 0
+-- Retrieval info: CONNECT: result 0 0 32 0 @result 0 0 32 0
+-- Retrieval info: GEN_FILE: TYPE_NORMAL mf_alt_subtr.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL mf_alt_subtr.inc FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL mf_alt_subtr.cmp TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL mf_alt_subtr.bsf FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL mf_alt_subtr_inst.vhd TRUE
+-- Retrieval info: LIB_FILE: lpm

cMIPS/altera/mf_alt_subtr_inst.vhd

+mf_alt_subtr_inst : mf_alt_subtr PORT MAP (
+		dataa	 => dataa_sig,
+		datab	 => datab_sig,
+		overflow	 => overflow_sig,
+		result	 => result_sig
+	);

cMIPS/altera/mf_altclkctrl.qip

+set_global_assignment -name IP_TOOL_NAME "ALTCLKCTRL"
+set_global_assignment -name IP_TOOL_VERSION "13.1"
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "mf_altclkctrl.vhd"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "mf_altclkctrl_inst.vhd"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "mf_altclkctrl.cmp"]

cMIPS/altera/mf_altclkctrl.vhd

+-- megafunction wizard: %ALTCLKCTRL%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: altclkctrl 
+
+-- ============================================================
+-- File Name: mf_altclkctrl.vhd
+-- Megafunction Name(s):
+-- 			altclkctrl
+--
+-- Simulation Library Files(s):
+-- 			
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 15.0.0 Build 145 04/22/2015 SJ Web Edition
+-- ************************************************************
+
+
+--Copyright (C) 1991-2015 Altera Corporation. All rights reserved.
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, the Altera Quartus II License Agreement,
+--the Altera MegaCore Function License Agreement, or other 
+--applicable license agreement, including, without limitation, 
+--that your use is for the sole purpose of programming logic 
+--devices manufactured by Altera and sold by Altera or its 
+--authorized distributors.  Please refer to the applicable 
+--agreement for further details.
+
+
+--altclkctrl CBX_AUTO_BLACKBOX="ALL" CLOCK_TYPE="Global Clock" DEVICE_FAMILY="Cyclone IV E" ENA_REGISTER_MODE="falling edge" USE_GLITCH_FREE_SWITCH_OVER_IMPLEMENTATION="OFF" clkselect ena inclk outclk
+--VERSION_BEGIN 15.0 cbx_altclkbuf 2015:04:15:19:11:38:SJ cbx_cycloneii 2015:04:15:19:11:39:SJ cbx_lpm_add_sub 2015:04:15:19:11:39:SJ cbx_lpm_compare 2015:04:15:19:11:39:SJ cbx_lpm_decode 2015:04:15:19:11:39:SJ cbx_lpm_mux 2015:04:15:19:11:39:SJ cbx_mgl 2015:04:15:20:18:26:SJ cbx_stratix 2015:04:15:19:11:39:SJ cbx_stratixii 2015:04:15:19:11:39:SJ cbx_stratixiii 2015:04:15:19:11:39:SJ cbx_stratixv 2015:04:15:19:11:39:SJ  VERSION_END
+
+ LIBRARY cycloneive;
+ USE cycloneive.all;
+
+--synthesis_resources = clkctrl 1 
+ LIBRARY ieee;
+ USE ieee.std_logic_1164.all;
+
+ ENTITY  mf_altclkctrl_altclkctrl_7ji IS 
+	 PORT 
+	 ( 
+		 clkselect	:	IN  STD_LOGIC_VECTOR (1 DOWNTO 0) := (OTHERS => '0');
+		 ena	:	IN  STD_LOGIC := '1';
+		 inclk	:	IN  STD_LOGIC_VECTOR (3 DOWNTO 0) := (OTHERS => '0');
+		 outclk	:	OUT  STD_LOGIC
+	 ); 
+ END mf_altclkctrl_altclkctrl_7ji;
+
+ ARCHITECTURE RTL OF mf_altclkctrl_altclkctrl_7ji IS
+
+	 SIGNAL  wire_clkctrl1_outclk	:	STD_LOGIC;
+	 SIGNAL  clkselect_wire :	STD_LOGIC_VECTOR (1 DOWNTO 0);
+	 SIGNAL  inclk_wire :	STD_LOGIC_VECTOR (3 DOWNTO 0);
+	 COMPONENT  cycloneive_clkctrl
+	 GENERIC 
+	 (
+		clock_type	:	STRING;
+		ena_register_mode	:	STRING := "falling edge";
+		lpm_type	:	STRING := "cycloneive_clkctrl"
+	 );
+	 PORT
+	 ( 
+		clkselect	:	IN STD_LOGIC_VECTOR(1 DOWNTO 0);
+		ena	:	IN STD_LOGIC;
+		inclk	:	IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+		outclk	:	OUT STD_LOGIC
+	 ); 
+	 END COMPONENT;
+ BEGIN
+
+	clkselect_wire <= ( clkselect);
+	inclk_wire <= ( inclk);
+	outclk <= wire_clkctrl1_outclk;
+	clkctrl1 :  cycloneive_clkctrl
+	  GENERIC MAP (
+		clock_type => "Global Clock",
+		ena_register_mode => "falling edge"
+	  )
+	  PORT MAP ( 
+		clkselect => clkselect_wire,
+		ena => ena,
+		inclk => inclk_wire,
+		outclk => wire_clkctrl1_outclk
+	  );
+
+ END RTL; --mf_altclkctrl_altclkctrl_7ji
+--VALID FILE
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+ENTITY mf_altclkctrl IS
+	PORT
+	(
+		inclk		: IN STD_LOGIC ;
+		outclk		: OUT STD_LOGIC 
+	);
+END mf_altclkctrl;
+
+
+ARCHITECTURE RTL OF mf_altclkctrl IS
+
+	SIGNAL sub_wire0	: STD_LOGIC ;
+	SIGNAL sub_wire1_bv	: BIT_VECTOR (1 DOWNTO 0);
+	SIGNAL sub_wire1	: STD_LOGIC_VECTOR (1 DOWNTO 0);
+	SIGNAL sub_wire2	: STD_LOGIC ;
+	SIGNAL sub_wire3	: STD_LOGIC ;
+	SIGNAL sub_wire4	: STD_LOGIC_VECTOR (3 DOWNTO 0);
+	SIGNAL sub_wire5_bv	: BIT_VECTOR (2 DOWNTO 0);
+	SIGNAL sub_wire5	: STD_LOGIC_VECTOR (2 DOWNTO 0);
+
+
+
+	COMPONENT mf_altclkctrl_altclkctrl_7ji
+	PORT (
+			clkselect	: IN STD_LOGIC_VECTOR (1 DOWNTO 0);
+			ena	: IN STD_LOGIC ;
+			inclk	: IN STD_LOGIC_VECTOR (3 DOWNTO 0);
+			outclk	: OUT STD_LOGIC 
+	);
+	END COMPONENT;
+
+BEGIN
+	sub_wire1_bv(1 DOWNTO 0) <= "00";
+	sub_wire1    <= To_stdlogicvector(sub_wire1_bv);
+	sub_wire2    <= '1';
+	sub_wire5_bv(2 DOWNTO 0) <= "000";
+	sub_wire5    <= To_stdlogicvector(sub_wire5_bv);
+	outclk    <= sub_wire0;
+	sub_wire3    <= inclk;
+	sub_wire4    <= sub_wire5(2 DOWNTO 0) & sub_wire3;
+
+	mf_altclkctrl_altclkctrl_7ji_component : mf_altclkctrl_altclkctrl_7ji
+	PORT MAP (
+		clkselect => sub_wire1,
+		ena => sub_wire2,
+		inclk => sub_wire4,
+		outclk => sub_wire0
+	);
+
+
+
+END RTL;
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: PRIVATE: clock_inputs NUMERIC "1"
+-- Retrieval info: CONSTANT: ENA_REGISTER_MODE STRING "falling edge"
+-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
+-- Retrieval info: CONSTANT: USE_GLITCH_FREE_SWITCH_OVER_IMPLEMENTATION STRING "OFF"
+-- Retrieval info: CONSTANT: clock_type STRING "Global Clock"
+-- Retrieval info: USED_PORT: inclk 0 0 0 0 INPUT NODEFVAL "inclk"
+-- Retrieval info: USED_PORT: outclk 0 0 0 0 OUTPUT NODEFVAL "outclk"
+-- Retrieval info: CONNECT: @clkselect 0 0 2 0 GND 0 0 2 0
+-- Retrieval info: CONNECT: @ena 0 0 0 0 VCC 0 0 0 0
+-- Retrieval info: CONNECT: @inclk 0 0 3 1 GND 0 0 3 0
+-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk 0 0 0 0
+-- Retrieval info: CONNECT: outclk 0 0 0 0 @outclk 0 0 0 0
+-- Retrieval info: GEN_FILE: TYPE_NORMAL mf_altclkctrl.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL mf_altclkctrl.inc FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL mf_altclkctrl.cmp TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL mf_altclkctrl.bsf FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL mf_altclkctrl_inst.vhd TRUE